Services

1. PCB Design, Schematic Capture & Layout

Our core work. Most of it is mixed-signal: an FPGA or microcontroller next to sensitive analog front-ends, clean power rails, and a fabric of signal-integrity constraints that have to be settled before routing starts.

• Cadence Allegro
• Altium
• 4 to 20+ layers
• Blind/buried vias, HDI

• Schematic capture: Cadence Allegro, Altium, OrCAD. Library management, BOM discipline
• Circuit analysis and design: analog front-ends, power supplies (switchers and LDOs), clocking trees, reset/brownout, level shifting, isolation
• PCB layout: multi-layer stackups including buried capacitance, controlled impedance, blind/buried vias, HDI. 4-layer to 20+ layers
• Simulation: LTspice for analog, thermal hand-analysis with FEA where the power density warrants it
• Design for manufacture: fabrication and assembly constraints applied while the layout is still movable, not after the quote comes back
• Fabrication: PCB manufacturing resource available — we can take a design from schematic to populated board without you chasing vendors

• Circuit design only (customer does layout)
• Full schematic + PCB layout
• Design review of an existing board (1 week, fixed scope)
• Failure analysis and debug on an existing product

2. Signal & Power Integrity, EMI/EMC

Boards fail in the chamber and in the field for reasons that were settled at stackup. We model them before that happens — and when a product is already built, we find out why it is misbehaving rather than guessing.

• Ansys SIwave
• Siemens HyperLynx
• IBIS / IBIS-AMI
• Pre- and post-layout

• Pre-layout constraint development: topology, termination, stackup and impedance targets fixed before routing starts
• Post-layout verification: SIwave and HyperLynx run on the real board, not on the intent
• Power integrity: PDN impedance targets, decoupling strategy, plane resonance and IR-drop analysis
• Signal integrity: reflection, crosstalk, timing and eye closure using IBIS and IBIS-AMI models
• 3D field solver analysis where the geometry stops behaving like a transmission line — connectors, via transitions, breakout regions
• EMI/EMC: design for pre-compliance before you step into the chamber
• Failure analysis: measurement on the bench, correlation back to the model, and the fix

• Pre-layout constraint study (1–2 weeks)
• Post-layout SI/PI verification of an existing design (1–2 weeks)
• PDN and decoupling review (1 week, fixed scope)
• Failure analysis and debug on a product already in the field

3. Functional Safety — FMEDA & FMEA Review (ISO 26262)

Safety-critical board and silicon designs live or die on diagnostic coverage. FMEDA — Failure Modes, Effects, and Diagnostic Analysis — is where that coverage gets proven to auditors.

• ISO 26262
• IEC 61508 / 62304 / DO-254
• Board and silicon level
• Pre-audit gap analysis

• FMEDA spreadsheets and reports for ASIL-A through ASIL-D parts
• Design FMEA and Process FMEA review — structure, ranking discipline, and whether the listed actions actually close the risk they claim to
• Failure rate (FIT) budgets per subsystem
• Diagnostic coverage modeling, including latent-fault detection
• Safety mechanisms: lockstep cores, ECC strategies, watchdog architectures, BIST
• Safety case artifacts: assumptions of use, safety goals, safety requirements traceability
• Pre-audit gap analysis — what your existing documentation is missing before the certification body arrives

• Review an existing FMEDA or FMEA and identify gaps (1–2 weeks)
• Build an FMEDA from scratch for a new board, IP or module (3–8 weeks)
• On-call safety engineer during an active certification cycle

4. Safety Soft-IP & Verification IP

Alongside the design services we license two catalogs: safety-instrumented soft-IP with the safety analysis already done, and independent verification IP written clean-room from the public protocol specifications.

• 182 safety blocks
• ASIL-B
• FMEDA + IP-XACT included
• 139 VIP · 55 shipping
• See the catalog →

• Safety Soft-IP: 182 blocks with published SPFM/LFM figures, FMEDA, IP-XACT descriptors and formal sign-off — the analysis ships with the block, not as a later invoice
• Subsystems: safety island, NPU island, coherent fabric (CHI), post-quantum cryptography
• Verification IP: 139 protocol VIP catalogued, 55 shipping today — BFMs, monitors and passive protocol checkers
• Independent second source: our VIP is written from the public specification, so it can genuinely disagree with your primary vendor’s VIP rather than share its assumptions
• Integration support: bringing a catalog block into your design, with its safety case intact

• License a block or a VIP (deliverables and terms under mutual NDA)
• Second-source verification of a protocol you already have a VIP for
• Custom safety instrumentation of an existing block

5. RISC-V / SoC Architecture

Our principal has been defining silicon for over two decades — from custom cores at IBM and Apple to full SoC architecture at APCON and Intensivate-era RISC-V work.

• Safety island
• NPU island
• Coherent fabric (CHI)
• Post-quantum crypto
• See the catalog →

• Core specifications: ISA profile selection, pipeline definition, microarchitecture trade-offs
• Cache and memory hierarchy design (L1/L2/L3, coherence protocol choice, MMU/PMP configuration)
• Custom ISA extensions for domain-specific workloads
• Full SoC integration: bus fabric (AXI, CHI, TileLink), NoC topology, power domains, clock domains
• Architecture reviews — does the proposed design actually meet the performance, power, and area targets, and if not, where’s the leak?
• Pre-RTL modeling (cycle-approximate SystemC or pure-Python)

• Design review (1 week, fixed scope)
• Architecture definition for a new core or SoC (1–3 months)
• Advisory retainer — monthly check-in + on-call for a team doing their own implementation

6. Verification & Emulation

Verification eats schedules. We’ve spent years pushing testbenches, formal, and emulation platforms to close coverage faster.

• SystemVerilog + UVM
• JasperGold / Synopsys Formal
• ZeBu & HAPS
• TLA+
• See the catalog →

• Simulation-based verification: SystemVerilog + UVM testbenches, constrained-random generation, functional coverage closure
• Formal verification: JasperGold, Synopsys Formal. Property specification, assume/assert strategy, bounded and unbounded proofs
• Specification-level verification: TLA+ models for protocol correctness before RTL exists
• Emulation bring-up: Synopsys ZeBu and HAPS platforms. Design partitioning, clock domain handling, DUT instrumentation, regression flows
• FPGA prototyping: Xilinx-based prototypes for software bring-up ahead of tape-out
• Tool ownership: Synopsys VCS and Verdi, Cadence Xcelium, waveform-first debug methodology

• Testbench audit — find coverage gaps in an existing environment (1–2 weeks)
• Formal property set for a new block (2–6 weeks)
• ZeBu/HAPS bring-up for a new SoC (4–12 weeks)
• TLA+ model for a contested protocol spec (1–3 weeks)

7. Technical Due Diligence

For VCs evaluating a hardware investment, acquirers inspecting a target, or boards that want a second opinion on their own team’s plans.

• Light — 1 week
• Standard — 2 weeks
• Deep — 3–4 weeks
• Written risk-ranked report

• Architecture soundness: does the proposed silicon or system actually do what the pitch claims?
• Execution risk: are the schedules realistic? Is the team sized for the work? What’s the critical path?
• IP review: freedom-to-operate check, open-source license exposure, third-party IP dependencies
• Team capability assessment: interviews with key engineers, code/RTL samples, tool proficiency
• Comparable analysis: how does this compare to what competitors are doing or have shipped?
• Written report: executive summary + detailed findings + risk-ranked recommendations

• Light DD — 1 week, documentation and interviews only
• Standard DD — 2 weeks, includes one-day site visit and deeper code/RTL inspection
• Deep DD — 3–4 weeks, includes running hands-on evaluation of the tech

Fixed-scope engagements

Short, bounded pieces of work with a defined deliverable and a known duration — the usual way a longer engagement starts. Each one ends in a written artifact you keep, whether or not the work continues.

All engagements by negotiation

Scope, rate, and terms tailored to the project. Short reviews, multi-month builds, fractional engineering — all on the table.